1. Field of the Invention
The present invention relates to an AD converter, and more particularly to a configuration of a voltage comparator having a sample hold which is used in a successive approximation AD converter.
2. Description of the Related Art
FIG. 2 shows the configuration of a conventional successive approximation AD converter. This AD converter is realized by a MOS integrated circuit, and comprises a voltage comparator 1, a successive approximation register 2, and a DA converter 3. The voltage comparator 1 has both a function for sampling an input analog signal and a function for performing a voltage comparison. The positive input terminal of the voltage comparator 1 is connected to a capacitor C1 serving as a sampling capacitor. An analog signal AIN to be subjected to AD conversion is input-into the positive input terminal of the voltage comparator 1 via a switch S1 and the capacitor C1. A connection point between the positive input terminal of the voltage comparator 1 and the capacitor C1 is biased to a reference voltage VR via a switch S6.
The negative input terminal of the voltage comparator 1 is connected to one end of a capacitor C2 and biased to the reference voltage VR via a switch S5. The other end of the capacitor C2 is biased to the reference voltage VR via switches S3, S4.
The successive approximation register 2 is connected to an output terminal of the voltage comparator 1, and holds an output signal from the voltage comparator 1. The DA converter 3 converts the data in the successive approximation register 2 into an analog signal. The output terminal of the DA converter 3 is connected to the positive input terminal of the voltage comparator 1 via a switch S2 and the capacitor C1.
The voltage comparator 1 used in the successive approximation AD converter described above is constituted as shown in FIG. 3, for example. Differential amplifiers 11, 12 and a final amplifier 13 are connected by multi-stage capacitive couplings. Switches S5 through S10 supplying the reference voltage VR are connected on each differential stage. The basic form of this circuit is disclosed in “Potential of MOS Technologies for Analog Integrated Circuits”, IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 3, June 1978, for example.
Further, the differential amplifiers 11, 12 used in the voltage comparator 1 are constituted as shown in FIG. 4, for example. A transistor 113 having a gate electrode serving as a positive input and a transistor 114 having a gate electrode serving as a negative input are connected in series respectively to transistors 111, 112 each having grounded gate electrodes, and the transistors 113, 114 are grounded via a bias transistor 115. The final amplifier 13 of the voltage comparator 1 has a configuration such as that shown in FIG. 5, for example, in which transistors 131 through 140 are wired.
Next, an operation of the conventional voltage comparator 1 shown in FIG. 3 will be described in reference to timing charts shown in FIGS. 8 and 9. The voltage comparator 1 performs an input signal sampling operation and a voltage comparing operation alternately. In FIG. 3, the symbol φ1 is annexed to switches that are ON when an input signal is sampled, and the symbol φ2 is annexed to switches that are ON when voltage comparison is performed. The timing chart of FIG. 8 shows a signal wave forms at points including the input of the comparator 1, the inputs of the differential amplifiers 11, 12, and the inputs and outputs of the final amplifier 13, in the conventional voltage comparator 1 in the case where a noise is not input to the comparator 1, the timing chart of FIG. 9 shows those in the case where a noise is input to the comparator 1. In the timing charts of FIGS. 8 and 9, an input signal is sampled during the first half period (φ1) and voltage comparison is performed during the last half period (φ2).
First, an input signal sampling operation shown in FIG. 8 will be described. At the timing of this operation, the switches S1, S3, S5, S6, S7, S8, S9, and S10 are ON, and the remaining switches S2, S4 are OFF. First, an input analog signal is stored in the capacitor C1. The voltage serving as a reference is the voltage VR supplied via the switches S5, S6.
Both of the input voltages of the differential amplifier 11 are the reference voltage VR, and the output voltage is a voltage produced by amplifying an offset voltage. The input terminals of the second stage differential amplifier 12 are connected to the input terminals of the differential amplifier 11 via the switches S5, S6, S7, S8, and hence the input voltages of this differential amplifier 12 are also the reference voltage VR. Likewise, the output voltage of the second stage differential amplifier 12 is also a voltage produced by amplifying an offset voltage, similarly to the first stage of the differential amplifier 11. The third stage is the same. Since the amplification stages are capacitively coupled in this manner and each stage is input with the reference voltage VR, the first stage offset voltage is not transmitted to the latter stages. Hence the offset voltage of the entire amplification circuit becomes the offset voltage of the final stage, i.e. the final amplifier 13. Thus with a three-stage configuration as shown in this example, the offset voltage calculated upon input can be considered as a fraction of the gain of the previous two stages, and hence can be reduced in magnitude considerably.
Next, a voltage comparison operation will be described. During the period of this operation, the switches S2, S4 annexed with the symbol φ2 in FIG. 3 are ON, and the other switches S1, S3, S5, S6, S7, S8, S9, S10 are OFF. The inputs of each differential stage (the differential amplifiers 11, 12 and the final amplifier 13) are removed from the reference voltage VR since the switches S15 through S20 are OFF. As a result, the differential amplifiers 11, 12 and the final amplifier 13 perform amplification in accordance with the variation in the inputs. Thus the comparison operation is performed.
As shown in FIG. 9, a pulsing noise may intrude immediately before the completion of sampling. In this case, the reference voltage VR is supplied to the inputs of the differential amplifiers 11, 12 and final amplifier 13 through the switches S5, S6, S7, S8, S9, S10, and hence has a time constant with the capacitors C1, C2, C3, C4, C5, C6. Therefore, the path that is charged from the reference voltage VR through the switches S5 through S10 cannot follow this noise. On the other hand, the response of the differential amplifiers 11, 12 and the final amplifier 13 is sometimes sufficiently fast.
In such a case, the differential amplifier 11 is not fixed to the reference voltage VR, and therefore executes amplification as shown in FIG. 9. The amplified noise is then output from the differential amplifier 11 and held in the capacitors C3, C4. For example, a voltage which is approximately equal to the voltage amplitude is generated. The sampling cycle may then end while such a large voltage is generated.
The differential amplifiers 11, 12 are designed to have an amplification factor of approximately ten to prevent the output voltage from saturating even when an offset voltage is present in order to increase the response speed, and are also designed such that the output amplitude is voltage-restricted to less than half of the supply voltage so as not to exceed the supply voltage following capacitive coupling and transmission to the next differential stage. When a comparison operation starts with a large voltage differential, since the output amplitude of the differential stage is restricted, the voltage differential cannot be eliminated, and hence the voltage comparator is fixed in a 0 or 1 state. As a result, the output of the AD converter outputs all 0 data or all 1 data.
Thus with a conventional AD converter, a disadvantage exists in that if a pulsing noise arises immediately before the completion of sampling, the output of the AD converter outputs all 0 data or all 1 data.